PI6ULS5V9515A

Product Description

The PI6ULS5V9515A is a CMOS integrated circuit intended for I²C bus and SMBus systems applications. The device contains two identical bidirectional opendrain buffer circuits that enable I²C and similar bus systems to be extended without degradation of system performance.

The PI6ULS5V9515A enables the system designer to isolate two halves of a bus for both voltage and capacitance, accommodating more I²C devices or longer trace length. It also permits extension of the I²C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus allowing two buses of 400 pF to be connected in an I²C application.

The PI6ULS5V9515A has an EN pin to turn the drivers on and off. This can be used to isolate a badly behaved slave on power-up until after the system powerup reset. It should never change state during an I²C-bus operation because disabling during a bus operation will hang the bus and enabling part way through a bus cycle could confuse the I²C-bus parts being enabled. The enable pin should only change state when the global bus and the repeater port are in an idle state to prevent system failures.

The output low levels for sides are approximately 0.5 V, but the input voltage of each internal buffer must be 70 mV lower (0.43V) or even more lower. When the output internally is driven low the low is not recognized as a low by the input.. This prevents a lockup condition from occurring when the input low condition is released.

Two or more PI6ULS5V9515A devices can’t be used in series. The PI6ULS5V9515A design does not allow this configuration. Since there is no direction pin, slightly different valid low-voltage levels are used to avoid lockup conditions between the input and the output of each repeater. A valid low applied at the input of a PI6ULS5V9515A will be propagated as a buffered low with a slightly higher value on the output. When this buffered low is applied to another PI6ULS5V9515Atype device in series, the second device does not recognize it as a valid low and will not propagate it as a buffered low again.

The device contains a power-up control circuit that sets an internal latch to prevent the output circuits from becoming active until Vcc is at a valid level (Vcc = 2.3 V).

As with the standard I²C system, pull-up resistors are required to provide the logic-high levels on the buffered bus. The PI6ULS5V9515A has standard open-collector configuration of the I²C bus. The size of these pull-up resistors depends on the system, but each side of the repeater must have a pull-up resistor. The device is designed to work with Standard mode and Fast mode I²C devices in addition to SMBus devices. Standard mode I²C devices only specify 3mA in a generic I²C system, where Standard mode devices and multiple masters are possible. Under certain conditions, higher termination currents can be used.

Features

• 2 channel, bidirectional buffer
• I²C-bus and SMBus compatible
• Operating supply voltage range of 2.3 V to 3.6 V
• Active HIGH repeater enable input
• Open-drain input/outputs
• Lock-up free operation
• Supports arbitration and clock stretching across the repeater
• Accommodates Standard-mode and Fast-mode I²Cbus devices and multiple masters
• Powered-off high-impedance I²C-bus pins
• 5.5 V tolerant I²C-bus and enable pins
• 0 Hz to 400 kHz clock frequency (the maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater)
• ESD protection exceeds 4KV HBM per JESD22- A114
• Package: MSOP-8, SOIC-8 and DFN2x3-8L