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PI7C9X2G303EL

3-Port, 3-Lane, ExtremeLo PCIe 2.0 Packet Switch

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Description

Similar to the role of PCI/PCIX Bridge in PCI/PCIX bus architecture, the function of PCI Express (PCIE) Switch is to expand the connectivity to allow more end devices to be reached by host controllers in PCIE serial interconnect architecture. The 3-lane PCIe Switch is in 3-port type configuration. It provides users the flexibility to expand or fan-out the PCI Express lanes based on their application needs.

In the PCI Express Architecture, the PCIE Switch forwards posted and non-posted requests, and completion packets in either downstream or upstream direction concurrently as if a virtual PCI Bridge is in operation on each port. By visualizing the port as a virtual Bridge, the Switch can be logically viewed as two-level cascaded multiple virtual PCI-to-PCI Bridges, where one upstream-port Bridge sits on all downstream-port Bridges. Similar to a PCI Bridge during enumeration, each port is given a unique bus number, device number, and function number by the initiating software. The bus number, device number, and function number are combined to form a destination ID for each specific port. In addition to that, the memory-map and IO address ranges are exclusively allocated to each port as well. After the software enumeration is finished, the packets are routed to the dedicated port based on the embedded address or destination ID. To ensure the packet integrity during forwarding, the Switch is not allowed to split the packets to multiple small packets or merge the received packets into a large transmit packet. Also, the IDs of the requesters and completers are kept unchanged along the path between ingress and egress port.

Feature(s)

  • 3-lane PCI Express® Gen 2 Switch with 3 PCI Express ports
  • Supports “Cut-through”(Default) as well as “Store and Forward” mode for packet switching
  • Peer-to-peer switching between any two downstream ports
  • 150 ns typical latency for packet routed through Switch without blocking
  • Integrated reference clock for downstream ports
  • Strapped pins configurable with optional EEPROM or SMBus
  • SMBus interface support
  • Compliant with System Management (SM) Bus, Version 1.0
  • Compliant with PCI Express Base Specification Revision 2.1
  • Compliant with PCI Express CEM Specification Revision 2.0
  • Compliant with PCI-to-PCI Bridge Architecture Specification Revision 1.2
  • Compliant with Advanced Configuration Power Interface (ACPI) Specification
  • Reliability, Availability and Serviceability
    。 Supports Data Poisoning and End-to-End CRC
    。 Advanced Error Reporting and Logging
    。 IEEE 1149.1 JTAG interface support
  • Advanced Power Saving
    。 Empty downstream ports are set to idle state to minimize power consumption
  • Link Power Management
    。 Supports L0, L0s, L1, L2, L2/L3Ready and L3 link power states
    。 Active state power management for L0s and L1 states
  • Device State Power Management
    。 Supports D0, D3Hot and D3Cold device power states
    。 3.3V Aux Power support in D3Cold power state
  • Port Arbitration: Round Robin (RR), Weighted RR and Time-based Weighted RR
  • Extended Virtual Channel capability
    。 Two Virtual Channels (VC) and Eight Traffic Class (TC) support
    。 Disabled VCs’ buffer is assigned to enabled VCs for resource sharing
    。 Independent TC/VC mapping for each port
    。 Provides VC arbitration selections: Strict Priority, Round Robin (RR) and Programmable Weighted RR
  • Supports Isochronous Traffic
    。 Isochronous traffic class mapped to VC1 only
    。 Strict time based credit policing
  • Supports up to 512-byte maximum payload size
  • Programmable driver current and de-emphasis level at each individual port
  • Support Access Control Service (ACS) for peer-to-peer traffic
  • Support Address Translation (AT) packet for SR-IOV application
  • Support OBFF and LTR
  • Low Power Dissipation: 650 mW typical in L0 normal mode
  • Industrial Temperature Range: -40o to 85oC
  • Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
  • Halogen and Antimony Free. “Green” Device (Note 3)
  • For automotive applications requiring specific change control (i.e. parts qualified to AEC-Q100/101/104/200, PPAP capable, and manufactured in IATF 16949 certified facilities), please contact us or your local Diodes representative. https://www.diodes.com/quality/product-definitions/
  • 136-pin aQFN 8mm x 8mm package

Product Specifications

Product Parameters

Ports 3
Lanes 3
Power 0.7 w
Latency 150 ns
Ambient or Junction Temperature (°C) -40 to 85
Compliance (Only Automotive supports PPAP) Standard

Technical Documents

Recommended Soldering Techniques

TN1.pdf

Additional Technical Documents are available upon request: 
Application information, Design tool model software, Design kits, Evaluation board, and Other technical documents

Request Documents
Orderable Part Number Status Package Environmental Compliance Packing Buy from Distributor /
Contact Sales
Request Samples
Qty. Carrier
PI7C9X2G303ELAZXE Obsolete V-QFN8080-136 GREEN 260 TRAY
PI7C9X2G303ELAZXEX Obsolete V-QFN8080-136 GREEN 3000 T&R
PI7C9X2G303ELBZXE Active V-QFN8080-136 TPGP 260 TRAY

PI7C9X2G303ELBZXE

Authorized Distributor Quantity Inventory Date Countries/Regions Buy Online
Avnet 413 12/5/2022 United States Buy Now
Mouser Electronics Inc. 199 12/5/2022 South America, North America, Asia, Europe, Middle East Buy Now
Request Sample
PI7C9X2G303ELBZXEX Active V-QFN8080-136 TPGP 3000 T&R Contact Sales Request Sample
PI7C9X2G303ELZXEX Obsolete V-QFN8080-136 GREEN 3000 T&R

Environmental Compliance Legend:
LFF: Pb-Free Finish and RoHS 5/6
TLFP: Totally Pb-Free Product and RoHS 6/6
LFGP: Pb-free Finish and Green Product, RoHS 5/6 and Halogen Free
TPGP: Totally Pb-Free and Green Product, RoHS 6/6 and Halogen Free
GREEN: Halogen-free and RoHS compliant
RoHS: RoHS compliant but NOT halogen-free