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Next Generation HiFlex® Ethernet Network Clock Generator

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Product Description

The PI6LC48S25A is an LC VCO based low phase noise design intended for 10GbE applications. Typical 10GbE usage assumes a 25MHz crystal input, while the PLL loop is used to generate the 156.25MHz and other Ethernet clock frequencies. An ad- ditional buffered crystal oscillator output is provided to serve as a low noise reference for other circuitry.

For Ethernet applications other than 10GbE, programmable dividers allow for simultaneous output of 312.5, 156.25, 125, 100, 50, and 25MHz. This device offers both pin selection and I2C interface to give more options to meet various system needs. 


  • 3.3V & 2.5V supply voltage
  • Crystal/CMOS input: 25 MHz
  • Differential input: 25MHz, 125MHz, and 156.25 MHz
  • Output frequencies: 312.5, 156.25, 125, 100, 50, 25MHz
  • 4 Output banks with selectable output signaling: LVPECL or LVDS
  • Low 0.3ps typical integrated phase noise design: 156.25MHz (12kHz to 20MHz)
  • PLL Bypass mode for test
  • Power supply noise rejection: -52 dBc typical @ VDD
  • Packaging (Pb-free & Green): 56-lead 8×8mm TQFN
  • Industrial temperature support: -40C to 85C 

Product Specifications

Product Parameters

Supply Voltage (V) 2.5, 3.3
Jitter RMS (ps) 0.3
Skew (PS) 0
Output Frequency (MHz) 25/ 50/ 100 / 125/ 156.25/ 312.5
Input Type(s) Crystal, CMOS, Differential
Number of Outputs 11
Supported Frequencies (MHz) 25, 50, 100, 125, 156.25, 312.5
Ambient or Junction Temperature (°C) -40 to 85

Technical Documents

Design tool model software

Application information

Evaluation Boards and User Guides

Recommended Soldering Techniques


Additional Technical Documents are available upon request:
Application information, Evaluation board, and Other technical documents

Request Documents
Orderable Part Number Status Package Environmental Compliance Packing Buy from Distributor /
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Request Samples
Qty. Carrier
PI6LC48S25AZBBIEX Active V-QFN8080H100-56 TPGP 2000 T&R Contact Sales Request Sample

Environmental Compliance Legend:
LFF: Pb-Free Finish and RoHS 5/6
TLFP: Totally Pb-Free Product and RoHS 6/6
LFGP: Pb-free Finish and Green Product, RoHS 5/6 and Halogen Free
TPGP: Totally Pb-Free and Green Product, RoHS 6/6 and Halogen Free
GREEN: Halogen-free and RoHS compliant
RoHS: RoHS compliant but NOT halogen-free

Product Change Notices (PCNs)

A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.

PCN # Issue Date Implementation Date Subject
PCN-2328 2018-04-12 2018-10-12 Device End of Life for tray packaging only



What is HiFlex® clock IC?

PI6LCxxxx is Pericom's newly developed high frequency, very low jitter clock generator family, which use high Q silicon VCO to dramatically reduce traditional PLL clock jitter. They are especially good for Telecom, Datacom, and Ethernet for phase jitter <=1 ps designs.  HiFlex Clock FInder tool

What is LVPECL clock and its termination?

LVPECL is Low Voltage Positive (supply) Emitter Couple Logic. Its voltage level is around 2V+/-400mV and the most use termination is 150 ohm pull-down at output pin and AC or DC coupling to an equivalent 100 ohm across pair at RX ASIC side. Check ASIC datasheet  to prevent double termination.