NOTE: Datasheet may not yet reflect updated package obsolescence/phase out status or Package Drawing. Please refer to the PRODUCT OPTIONS tab for the most up to date package options and drawings. Please refer to PCN/PDN tabs for most current package obsolescence/phase out status.
Log in or register
to manage email notifications about changes to datasheets or PCNs for this part.
PI6CDBL402B is a PCIe 3.0 compliant high-speed, low-noise differential clock buffer designed to be companion to PCIe 3.0 clock generator. It is backward compatible with PCIe 1.0 and 2.0 specification. The device distributes the differential SRC clock from PCIe 3.0 clock generator to four differential pairs of clock outputs either with or without PLL. The clock outputs are controlled by input selection of PWRDWN# and SMBus, SCLK and SDA.
Phase jitter filter for PCIe 3.0/ 2.0/ 1.0 application
Low power consumption with independent output power supply 1.8V~3.3V
Environmental Compliance Legend: LFF: Pb-Free Finish and RoHS 5/6 TLFP: Totally Pb-Free Product and RoHS 6/6 LFGP: Pb-free Finish and Green Product, RoHS 5/6 and Halogen Free TPGP: Totally Pb-Free and Green Product, RoHS 6/6 and Halogen Free GREEN: Halogen-free and RoHS compliant RoHS: RoHS compliant but NOT halogen-free