Diodes Incorporated
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PI6C20800B

PCI Express® 3.0 1:8 HCSL Clock Buffer

NOTE: Datasheet may not yet reflect updated package obsolescence/phase out status or Package Drawing. Please refer to the BUY NOW tab for the most up to date package options and drawings. Please refer to PCN/PDN tabs for most current package obsolescence/phase out status.
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Product Description

PI6C20800B is a PCIe 3.0 compliant, high-speed, low-noise differential clock buffer designed to be a companion to PCI Express 3.0 clock generator for Intel server chipsets. The device distributes the differential SRC clock from PCIe clock generator to eight differential pairs of clock outputs either with or without PLL. The input SRC clock can be divided by 2 when SRC_DIV# is LOW. The clock outputs are controlled by input selection of SRC_STOP#, PWRDWN# and SMBus, SCLK and SDA. When input of either SRC_STOP# or PWRDWN# is LOW, the output clocks are Tristated. When PWRDWN# is LOW, the SDA and SCLK inputs must be Tristated.

Features

  • Phase jitter filter for PCIe 3.0 application
  • Eight Pairs of Differential Clocks
  • Low skew < 50ps (PI6C20800B), <60ps (PI6C20800BI)
  • Low Cycle-to-cycle jitter < 60ps
  • Output Enable for all outputs
  • Outputs Tristate control via SMBus
  • Power Management Control
  • Programmable PLL Bandwidth
  • PLL or Fanout operation
  • 3.3V Operation
  • Industrial Temperature Option - PI6C20800BI
  • Packaging (Pb-Free & Green):
    • 48-Pin TSSOP (A)

Product Specifications

Product Parameters

Compliance (Only Automotive(Q) supports PPAP) Standard
Function PCIe clock buffer
Number of Outputs 8
Output Type(s) HCSL
Maximum Output Frequency (MHz) 100
Additive Jitter (ps) 60
Supply Voltage (V) 3.3
Input Type(s) HCSL
Skew (PS) 50
Ambient or Junction Temperature (°C) -40 to 85

Technical Documents

Application Information

Recommended Soldering Techniques

TN1.pdf

Product Change Notices (PCNs)

A PCN may only apply to specific orderable part numbers in this datasheet. Please refer to the corresponding PCN to see the exact orderable part number(s) affected.

PCN # Issue Date Implementation Date Subject
PCN-2327 (Advance Notice) 2018-04-20 2020-11-11 Fab Porting from Global Foundries to MagnaChip, Assembly Site Transfer, and Bond Wire Change