PI6C20800 (Obsolete)

Product Description

PI6C20800 is a high-speed, low-noise differential clock buffer designed to be a companion to PI6C410B. The device distributes the differential SRC clock from PI6C410B to eight differential pairs of clock outputs either with or without PLL.

The input SRC clock can be divided by 2 when SRC_DIV# is LOW. The clock outputs are controlled by input selection of SRC_STOP#, PWRDWN# and SMBus, SCLK and SDA.

When input of either SRC_STOP# or PWRDWN# is LOW, the output clocks are Tristated. When PWRDWN# is LOW, the SDA and SCLK inputs must be Tristated.

Features

• Eight Pairs of Differential Clocks
• Low skew < 50ps Low
• Cycle-to-cycle jitter < 50ps
• Output Enable for all outputs
• Outputs Tristate control via SMBus
• Power Management Control
• Programmable PLL Bandwidth
• PLL or Fanout operation
• 3.3V Operation
• 100-200 MHz PLL Mode Operation
• 100-400 MHz Bypass Mode Operation
• Packaging (Pb-Free & Green):
  — 48-Pin SSOP (V)
  — 48-Pin TSSOP (A)