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The 74HCT595 is an high speed CMOS device that is
designed to be pin compatable with 74LS low power
An eight bit shift register accpets data from the serial input
(DS) on each positive transition of the shift register clock
(STCP). When asserted low the reset function ( ) sets
all shift register values to zero and is indepent of all clocks.
Data from the input serial shift register is placed in the
output register with a rising pulse on the storages resister
clock (SHCP). With the output enable asserted low
the 3-state outputs Q0-Q7 become active and present th
All registers capture data on rising edge and change output
on the falling edge. If both clocks are connected together
the input shift register is always one clock cycle ahead of
the output register.
General Purpose Logic
Serial to Parallel Data conversion
Capture and hold data for extended periods of time.
Allow simple serial bit streams from a microcontroller
to control as many peripheral lines as needed.