Log in or register
to manage email notifications about changes to datasheets or PCNs for this part.
The 74HC594 is a high speed CMOS device.
An eight bit shift register accpets data from the serial input
(DS) on each positive transition of the shift register clock
(SHCP). When asserted low the shift regisister reset
function ( ) sets all shift register values to zero and is
indepent of all clocks. Also when asserted low the storage
register reset function ( ) sets all shift register values to
zero and is indepent of all clocks
Data from the input serial shift register is placed in the
output register with a rising pulse on the storages resister
clock.(STCP). The storage resister includes output Q7S
which is used for cascading information between devices.
As the information moves into the storage register, it is
asserted on the push-pull outputs Q0-Q7.
All registers capture data on rising edge and change output
on the falling edge. If both clocks are connected together
the input shift register is always one clock cycle ahead of
the output register.
General Purpose Logic
Serial to Parallel Data conversion
Capture and hold data for extended periods of time.
Allow simple serial bit streams from a microcontroller
to control as many peripheral lines as needed.
Wide array of products such as:
- Computer peripherals
- Industrial control