Dual 3-State Buffer OE LOW
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The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP2G126 is a dual 3-State Buffer. Each buffer has an individual output enable pin while asserted LOW will place the output in a high impedance state. The device is designed for operation over a power supply range of 0.8 V to 3.6 V. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down.
| Function | Buffer |
|---|---|
| Type | Buffers/Inverters/Transceivers |
| Compliance (Only Automotive supports PPAP) | Standard |
| Channels | 2 |
| Family | AUP |
| VCC Min (V) | 0.8 |
| VCC Max (V) | 3.6 |
| Input Type | Standard CMOS |
| Output Type | 3-State |
| Output Current (mA) | 4 |
